Electrostatic discharge (ESD) generally refers to the sudden and transient electric current flowing between two objects with different potentials, the different potentials being caused by static charge accumulation. ESD events have been modeled by various standards bodies for compliance testing purposes. These ESD event models include the American National Standards Institute (ANSI) model and the ESD Association's Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM). These models typically specify certain ESD event circuit models, each including a charging capacitor that stores the accumulated static charge to a certain ESD voltage level and a current limiting resistor to mimic the resistance in the ESD discharge path. During an ESD event, the two terminals of the charged capacitor are brought in contact with any two I/O pins of an integrated circuit (IC), the discharge current flows there through, and the static charge is neutralized.
An integrated circuit is susceptible to ESD strikes during fabrication, testing, packaging, transportation, and use. Accordingly, on-chip ESD protection circuits are imperative for an IC to achieve reasonable stability. The ever-shrinking IC process technologies that enable very high-frequency operations are generally more vulnerable to ESD events because of their small fabrication geometry. However, the conventional ESD protection methods generally introduce excessive parasitic effect, which substantially limit the performance of the high-speed input and output ports leaving a very stringent design trade-off between the IC's performance and the IC's reliability.
Conventional ESD methods for integrated circuits use devices such as diodes, silicon-controlled rectifiers (SCRs), grounded-gate n-channel MOSFETs (ggNMOSs). These methods protect the internal circuits by shunting the ESD current to ground or power supply rails during ESD event, where the potentials between the power supply rails are clamped using power clamps. Such ESD devices introduce certain parasitic impedance into the circuit being protected. This parasitic impedance could be utilized as a matching element. However, for high frequency analog and digital applications in the RF, microwave and millimeter-wave regime, the distributed effects of these conventional protection structures becomes significant. These effects can distort and deteriorate the interested signal being processing and bring about poor performance or even malfunction of the circuits being protected.
Consequently, different ESD protection methods need to be developed for high frequency I/O ports in integrated circuits, at which the distributed effects of the circuit devices are significant. Thus, what is needed is a scheme of distributed ESD protection devices to absorb the parasitic effects of the protection devices in a transmission line. Transmission lines can be employed to exhibits certain desirable impedance to the high frequency signal while bypass the ESD current to ESD protection devices or ground. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background of the disclosure.